Verilog for FPGA and ASIC Design (Deutsch)/(English)

Course Description

Verilog for FPGA Design prepares the engineer for practical project readiness for FPGA designs. While the emphasis is on the practical Verilog-to-hardware flow for FPGA devices, this module also provides the essential foundation needed by ASIC and FPGA designers wishing to apply the more advanced features of Verilog covered in the next module. Delegates targeting FPGAs will take away a flexible project infra-structure which includes a set of scripts, example designs, modules and constraint files to use, adapt and extend on their own projects.

Day 1:
- Introduction to VLSI world
- VLSI flow from Design till Fabrication
- Hello world
- Design Entities
- Processes
- Synthesising Combinational Logic

Day 2:
- Synthesiable or not Synthesiable
- Types
- Synthesis of Arithmetic
- Synthesising Sequential Logic

Day 3:
- FSM types and Synthesis
- Memories
- Reports
- IP and reuse
- PCB constrains
- Tips and Tricks

Prerequisites

Kursprogramm auf Anforderung

Target Group

New electrical engineers who wish to become skilled in the practical use of Verilog for FPGA or ASIC design.

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