UVM verification methodology for SoC and FPGA (Deutsch)/(English)

Course Description

The UVM (Universal Verification Methodology) course covers: Capability from writing small function coverage solutions to a robust methodology for big designs. Harness SystemVerilog functional coverage capabilities to a methodology that can cover full chip verification. UVM is writing functional coverage code that will be modular, scalable and easy to reuse. The capability to plan top bottom, from architecture level and zoom in. be able to breakdown the work to reasonable pieces generate working plan and execute.

Day 1:
- Introduction to UVM
- Architecture Level
- Transaction-Level Modeling (TLM)
- Generating Agents
- Monitors and Reporting
- Checkers and Scoreboards

Day 2:
- Effective Functional Coverage
- Scalable Random Stimulus Generation
- Factory and Configuration
- Objections
- Sequences

Day 3:
- Layered Sequences and Agents
- Events and Barriers
- Advanced Sequencer Topics
- UVM Register Layer
- Advanced Register Topics
- Callbacks and Heartbeat
- HIL - Hardware In the Loop
- Integration and closure

Prerequisites

Kursprogramm auf Anforderung

Target Group

ASIC/FPGA Verification Eng, which deploy the SystemVerilog course.

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