ARM / i.MX 6 (Deutsch)/(English)

Course Description

This 3 day course offers coverage of i.MX6x Family and its Target applications, Device architecture, Image Processing Unit (IPU) Architecture and Operation, Multi ARM Cortex Cores operation and Synchronization, Video Processing Unit Operation and design Considerations. I.MX6x New IP Blocks, Security, IOMUXING and Audio Interfaces. It includes coverage of System Memory Organization, Memory Types, DDR3 Interface and Operation, Boot Modes and Chip Low-power operation. It also covers, System Resets, Power-up sequence and System Initialization.

Course Content

  • Introduction to i.MX6 Family
    • Main Features and Road Map
    • From ARM9 to Cortex A9 MP
    • Qualification tiers (industrial, commercial, automotive, custom)
    • Freescale’s product longevity program
  • Target Markets Applications
    • General embedded
    • Medical
    • Tablet and eReader
    • Auto infotainment
    • Home energy
    • Real products example
  • i.MX6 Series Overview
    • iMX6 solo, solo lite, dual, dual lite, quad core comparison and main features
    • Multi-Cores needs & associated use cases
    • Cortex A9 versus Cortex A8
  • Device Architecture Overview
    • iMX6 devices block diagrams (core and accelerators)
    • Video Capabilities and SW codecs (standards, performance)
    • Graphics capabilities (2D & 3D, openGL vs openVG, openCL support, GPU performance with iMX family)
    • Display support (display resolution, multiple display support)
    • Multimedia processing chain (integration of ARM core, IPU, VPU, and GPU)
    • Memory and mass storage interfaces (NAND, EIM, LPDDR2/3, serial ePROM/serial NAND, SD/MMC, SATA)
    • General purpose connectivity (USB, Ethernet Controller, PCI-E)
    • Development platforms for iMX6 (Sabre light, Sabre tablet, quick start board, System on a module)
    • iMX6 power consumption & power saving techniques
    • Freescale PMIC features
  • i.MX6 Dual/Quad ARM Cortex A9 MP core platform
    • introduction to ARM Architecture
    • Platform overview (Core, Neon, private timer, watch dog, L1 Cache, L2 cache, SCU, GIC, CoreSight debug)
    • Platform configuration (single, dual. Quad and SCU configuration, endian support, memory parity error support)
  • Clocking, Reset & Power
    • Performance and power (process, voltage and temperature, low power design, state retention power gating, dynamic voltage and frequency scaling)
    • Clocks and Reset (CCM, SRC, GPC, power supplies)
  • Core Platform Sub-Blocks Details
    • Cortex A9 MP instruction set and pipeline description
    • MMU and TLBs
    • Cache coherency
    • MPE-NEON
    • GIC
    • TrustZone
    • PL310
    • CoreSight components (DAP, PTM, ETB)
    • Memory mapping (size, allocation, region, bandwidth calculation, optimization and considerations)
    • External Memories (MMDC, Raw NAND Flash controller, WEIM, DMA support)
  • i.MX6 Multimedia
    • Image Processing Unit (IPU)
    • Video Processing Unit (VPU)
    • Graphics Architecture (GPU)
  • IP Deep Dive
    • i.MX6 new IP Blocks
    • Security Architecture
    • Boot Modes
    • Input/Output
    • Audio Related Interfaces
  • Overview Freescale i.MX6 Software Release
    • i.MX6 Linux Software Release
    • i.MX6 Android Software Release
    • Board Support Package (BSP)


A basic understanding of micro-controllers is mandatory. Due to the high degree of functionality and integration of this device, the student is encouraged to gain some familiarity beforehand by reviewing current documentation for this product.

Target Group

System designer, System programmer, Application programmer, Embedded programmer and System tester

Course Material

  • Supporting Documents

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